# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Clock Out Control Module Binding

maintainers:
  - Sugar Zhang <sugar.zhang@rock-chips.com>

description: |
  This add support switch for clk-bidirection which located
  at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
  and these config maybe located in many pieces of GRF,
  which hard to addressed in one single clk driver. so, we add
  this simple helper driver to address this situation.

  In order to simplify implement and usage, and also for safety
  clk usage (avoid high freq glitch), we set all clk out as disabled
  (which means Input default for clk-bidrection) in the pre-stage,
  such boot-loader or init by HW default. And then set a safety freq
  before enable clk-out, such as "assign-clock-rates" or clk_set_rate
  in drivers.

properties:
  compatible:
    enum:
      - rockchip,clk-out

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  clocks:
    maxItems: 1
    description: parent clocks.

  power-domains:
    maxItems: 1

  clock-output-names:
    maxItems: 1

  rockchip,bit-shift:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Defines the bit shift of clk out enable.

  rockchip,bit-set-to-disable:
    type: boolean
    description: |
      By default this clock sets the bit at bit-shift to enable the clock.
      Setting this property does the opposite: setting the bit disable
      the clock and clearing it enables the clock.

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"
  - clock-output-names
  - rockchip,bit-shift

additionalProperties: false

examples:
  # Clock Provider node:
  - |
    mclkin_sai0: mclkin-sai0 {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <12288000>;
        clock-output-names = "mclk_sai0_from_io";
    };

    mclkout_sai0: mclkout-sai0@ff040070 {
        compatible = "rockchip,clk-out";
        reg = <0 0xff040070 0 0x4>;
        clocks = <&cru MCLK_SAI0_OUT2IO>;
        #clock-cells = <0>;
        clock-output-names = "mclk_sai0_to_io";
        rockchip,bit-shift = <4>;
    };

  # Clock mclkout Consumer node:
  - |
    ext_codec {
        clocks = <&mclkout_sai0>;
        clock-names = "mclk";
        assigned-clocks = <&mclkout_sai0>;
        assigned-clock-rates = <12288000>;
        pinctrl-names = "default";
        pinctrl-0 = <&i2s0m0_mclk>;
    };

  # Clock mclkin Consumer node:
  - |
    ext_codec {
        clocks = <&mclkin_sai0>;
        clock-names = "mclk";
        assigned-clocks = <&cru CLK_SAI0>;
        assigned-clock-parents = <&mclkin_sai0>;
        pinctrl-names = "default";
        pinctrl-0 = <&i2s0m0_mclk>;
    };
