# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM architected timer

maintainers:
  - Marc Zyngier <marc.zyngier@arm.com>
  - Mark Rutland <mark.rutland@arm.com>
description: |+
  ARM cores may have a per-core architected timer, which provides per-cpu timers,
  or a memory mapped architected timer, which provides up to 8 frames with a
  physical and optional virtual timer per frame.

  The per-core architected timer is attached to a GIC to deliver its
  per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
  to deliver its interrupts via SPIs.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - arm,cortex-a15-timer
          - enum:
              - arm,armv7-timer
      - items:
          - enum:
              - arm,armv7-timer
      - items:
          - enum:
              - arm,armv8-timer

  interrupts:
    items:
      - description: secure timer irq
      - description: non-secure timer irq
      - description: virtual timer irq
      - description: hypervisor timer irq

  clock-frequency:
    description: The frequency of the main counter, in Hz. Should be present
      only where necessary to work around broken firmware which does not configure
      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
      strongly discouraged; fix your firmware unless absolutely impossible.

  always-on:
    type: boolean
    description: If present, the timer is powered through an always-on power
      domain, therefore it never loses context.

  allwinner,erratum-unknown1:
    type: boolean
    description: Indicates the presence of an erratum found in Allwinner SoCs,
      where reading certain values from the counter is unreliable. This also
      affects writes to the tval register, due to the implicit counter read.

  fsl,erratum-a008585:
    type: boolean
    description: Indicates the presence of QorIQ erratum A-008585, which says
      that reading the counter is unreliable unless the same value is returned
      by back-to-back reads. This also affects writes to the tval register, due
      to the implicit counter read.

  hisilicon,erratum-161010101:
    type: boolean
    description: Indicates the presence of Hisilicon erratum 161010101, which
      says that reading the counters is unreliable in some cases, and reads may
      return a value 32 beyond the correct value. This also affects writes to
      the tval registers, due to the implicit counter read.

  arm,cpu-registers-not-fw-configured:
    type: boolean
    description: Firmware does not initialize any of the generic timer CPU
      registers, which contain their architecturally-defined reset values. Only
      supported for 32-bit systems which follow the ARMv7 architected reset
      values.

  arm,no-tick-in-suspend:
    type: boolean
    description: The main counter does not tick when the system is in
      low-power system suspend on some SoCs. This behavior does not match the
      Architecture Reference Manual's specification that the system counter "must
      be implemented in an always-on power domain."

required:
  - compatible

additionalProperties: false

oneOf:
  - required:
      - interrupts
  - required:
      - interrupts-extended

examples:
  - |
    timer {
      compatible = "arm,cortex-a15-timer",
             "arm,armv7-timer";
      interrupts = <1 13 0xf08>,
             <1 14 0xf08>,
             <1 11 0xf08>,
             <1 10 0xf08>;
      clock-frequency = <100000000>;
    };

...
